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ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
13 years 6 months ago
Evolution of thread-level parallelism in desktop applications
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...
ISPDC
2010
IEEE
13 years 6 months ago
Resource-Aware Compiler Prefetching for Many-Cores
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
George C. Caragea, Alexandros Tzannes, Fuat Keceli...
TSP
2008
132views more  TSP 2008»
13 years 6 months ago
On Doubly Selective Channel Estimation Using Superimposed Training and Discrete Prolate Spheroidal Sequences
Abstract--Channel estimation and data detection for frequencyselective time-varying channels are considered using superimposed training. We employ a discrete prolate spheroidal bas...
Shuangchi He, Jitendra K. Tugnait
JOCN
2010
70views more  JOCN 2010»
13 years 6 months ago
Optimizing Design Efficiency of Free Recall Events for fMRI
■ Free recall is a fundamental paradigm for studying memory retrieval in the context of minimal cue support. Accordingly, free recall has been extensively studied using behavior...
Ilke Öztekin, Nicole M. Long, David Badre
MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
13 years 6 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...