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» Comparison of Hardware and Software Cache Coherence Schemes
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ICPP
1999
IEEE
13 years 11 months ago
Optimization of Instruction Fetch for Decision Support Workloads
Instruction fetch bandwidth is feared to be a major limiting factor to the performance of future wide-issue aggressive superscalars. In this paper, we focus on Database applicatio...
Alex Ramírez, Josep-Lluis Larriba-Pey, Carl...
ISVLSI
2006
IEEE
114views VLSI» more  ISVLSI 2006»
14 years 1 months ago
A Low Power Lookup Technique for Multi-Hashing Network Applications
Many network security applications require large virus signature sets to be maintained, retrieved, and compared against the network streams. Software applications frequently fail ...
Ilhan Kaya, Taskin Koçak
SPAA
2006
ACM
14 years 1 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
ECRTS
2010
IEEE
13 years 8 months ago
Making DRAM Refresh Predictable
Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Sched...
Balasubramanya Bhat, Frank Mueller
CASES
2003
ACM
14 years 23 days ago
A low-power accelerator for the SPHINX 3 speech recognition system
Accurate real-time speech recognition is not currently possible in the mobile embedded space where the need for natural voice interfaces is clearly important. The continuous natur...
Binu K. Mathew, Al Davis, Zhen Fang