151 search results - page 7 / 31 » Comparison of Hardware and Software Cache Coherence Schemes |
ICPP
2007
IEEE
14 years 1 months ago
2007
IEEE
Ever-increasing memory footprint of applications and increasing mainstream popularity of shared memory parallel computing motivate us to explore memory compression potential in di...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
Data-race freedom is a valuable safety property for multithreaded programs that helps with catching bugs, simplifying memory consistency model semantics, and verifying and enforci...
HIPEAC
2010
Springer
13 years 5 months ago
2010
Springer
We propose a new design for an energy-efficient hardware transactional memory (HTM) system for power-aware embedded devices. Prior hardware transactional memory designs proposed a ...
IEEEPACT
2009
IEEE
13 years 5 months ago
2009
IEEE
Abstract--Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current...
CAV
1998
Springer
13 years 11 months ago
1998
Springer
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...