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ATAL
2006
Springer
13 years 11 months ago
Designing agent chips
We outline meta-encoding schemas for compiling nonmonotonic logic theories into Verilog HDL (Hardware Description Language) descriptions. These descriptions can be synthesized int...
Insu Song, Guido Governatori
COLING
1996
13 years 9 months ago
Top-Down Predictive Linking and Complex-Feature-Based Formalisms
Automatic compilation of the linking relation employed in certain parsing algorithms for context-free languages is examined. Special problems arise in the extension of these algor...
James Kilbury
APIN
2000
155views more  APIN 2000»
13 years 7 months ago
Defeasible Logic on an Embedded Microcontroller
Defeasible logic is a system of reasoning in which rules have exceptions, and when rules conflict, the one that applies most specifically to the situation wins out. This paper repo...
Michael A. Covington
PADL
2009
Springer
14 years 8 months ago
Declarative Network Verification
Abstract. In this paper, we present our initial design and implementation of a declarative network verifier (DNV). DNV utilizes theorem proving, a well established verification tec...
Anduo Wang, Prithwish Basu, Boon Thau Loo, Oleg So...
CACM
2010
120views more  CACM 2010»
13 years 7 months ago
seL4: formal verification of an operating-system kernel
We report on the formal, machine-checked verification of microkernel from an abstract specification down to its C implementation. We assume correctness of compiler, assembly code,...
Gerwin Klein, June Andronick, Kevin Elphinstone, G...