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ICS
1999
Tsinghua U.
14 years 1 months ago
Software trace cache
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
Alex Ramírez, Josep-Lluis Larriba-Pey, Carl...
SIGMETRICS
1996
ACM
118views Hardware» more  SIGMETRICS 1996»
14 years 28 days ago
Integrating Performance Monitoring and Communication in Parallel Computers
A large and increasing gap exists between processor and memory speeds in scalable cache-coherent multiprocessors. To cope with this situation, programmers and compiler writers mus...
Margaret Martonosi, David Ofelt, Mark Heinrich
AOSD
2009
ACM
14 years 24 days ago
The dataflow pointcut: a formal and practical framework
Some security concerns are sensitive to flow of information in a program execution. The dataflow pointcut has been proposed by Masuhara and Kawauchi in order to easily implement s...
Dima Alhadidi, Amine Boukhtouta, Nadia Belblidia, ...
CGO
2004
IEEE
14 years 16 days ago
Exposing Memory Access Regularities Using Object-Relative Memory Profiling
Memory profiling is the process of characterizing a program's memory behavior by observing and recording its response to specific input sets. Relevant aspects of the program&...
Qiang Wu, Artem Pyatakov, Alexey Spiridonov, Easwa...
EUROPAR
2006
Springer
14 years 13 days ago
Multi-dimensional Kernel Generation for Loop Nest Software Pipelining
Single-dimension Software Pipelining (SSP) has been proposed as an effective software pipelining technique for multi-dimensional loops [16]. This paper introduces for the first tim...
Alban Douillet, Hongbo Rong, Guang R. Gao