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125
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DATE
2004
IEEE
114views Hardware» more  DATE 2004»
15 years 6 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
116
Voted
SAC
2010
ACM
15 years 9 months ago
A real-time architecture design language for multi-rate embedded control systems
This paper presents a language dedicated to the description of the software architecture of complex embedded control systems. The language relies on the synchronous approach but e...
Julien Forget, Frédéric Boniol, Davi...
IPPS
2002
IEEE
15 years 7 months ago
A Performance Optimization Framework for Compilation of Tensor Contraction Expressions into Parallel Programs
This paper discusses a program synthesis system to facilitate the generation of high-performance parallel programs for a class of computations encountered in quantum chemistry and...
Gerald Baumgartner, David E. Bernholdt, Daniel Coc...
129
Voted
ISPDC
2008
IEEE
15 years 9 months ago
A Runtime System Architecture for Ubiquitous Support of OpenMP
In this work we present the runtime architecture of the OMPi OpenMP compiler. OMPi is a source-to-source C translator featuring a portable, modular and extensible runtime system. ...
Giorgos Ch. Philos, Vassilios V. Dimakopoulos, Pan...
136
Voted
FPL
2009
Springer
154views Hardware» more  FPL 2009»
15 years 7 months ago
Compiler assisted runtime task scheduling on a reconfigurable computer
Multitasking reconfigurable computers with one or more reconfigurable processors are being used increasingly during the past few years. One of the major challenges in such systems...
Mojtaba Sabeghi, Vlad Mihai Sima, Koen Bertels