Abstract Deciding which computer architecture provides the best performance for a certain program is an important problem in hardware design and benchmarking. While previous approa...
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
Designing MOS decoupling capacitors (DECAPs) in nanotechnologies provides many challenges due to the existing trade-offs among transient time response behavior, area, and gate lea...
Abstract. In this paper, we propose a novel hierarchical routing protocol for a large wireless sensor network (WSN) wherein sensors are arranged into a multi-layer architecture wit...
This paper proposes a novel approach for rank level fusion which gives improved performance gain verified by experimental results. In the absence of ranked features and instead of...