1008 search results - page 26 / 202 » Compiler Technology for Two Novel Computer Architectures |
IDA
2009
Springer
14 years 3 months ago
2009
Springer
Abstract Deciding which computer architecture provides the best performance for a certain program is an important problem in hardware design and benchmarking. While previous approa...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
VLSID
2009
IEEE
14 years 9 months ago
2009
IEEE
Designing MOS decoupling capacitors (DECAPs) in nanotechnologies provides many challenges due to the existing trade-offs among transient time response behavior, area, and gate lea...
ICCSA
2005
Springer
14 years 2 months ago
2005
Springer
Abstract. In this paper, we propose a novel hierarchical routing protocol for a large wireless sensor network (WSN) wherein sensors are arranged into a multi-layer architecture wit...
CVPR
2007
IEEE
14 years 10 months ago
2007
IEEE
This paper proposes a novel approach for rank level fusion which gives improved performance gain verified by experimental results. In the absence of ranked features and instead of...