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» Compiler Technology for Two Novel Computer Architectures
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HPCA
2007
IEEE
14 years 8 months ago
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications
Chip multiprocessors with multiple simpler cores are gaining popularity because they have the potential to drive future performance gains without exacerbating the problems of powe...
Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlk...
SPAA
2004
ACM
14 years 1 months ago
Fighting against two adversaries: page migration in dynamic networks
Page migration is one of the fundamental subproblems in the framework of data management in networks. It occurs in a distributed network of processors sharing one indivisible memo...
Marcin Bienkowski, Miroslaw Korzeniowski, Friedhel...
IEEECIT
2010
IEEE
13 years 7 months ago
CFCSS without Aliasing for SPARC Architecture
With the increasing popularity of COTS (commercial off the shelf) components and multi-core processor in space and aviation applications, software fault tolerance becomes attracti...
Chao Wang, Zhongchuan Fu, Hongsong Chen, Wei Ba, B...
HIPC
2007
Springer
14 years 2 months ago
Channel Adaptive Real-Time MAC Protocols for a Two-Level Heterogeneous Wireless Network
Abstract. Wireless technology is becoming an attractive mode of communication for real-time applications in typical settings such as in an industrial setup because of the tremendou...
Kavitha Balasubramanian, G. Sudha Anil Kumar, G. M...
ICMCS
2005
IEEE
104views Multimedia» more  ICMCS 2005»
14 years 2 months ago
A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
Grzegorz Pastuszak