1008 search results - page 8 / 202 » Compiler Technology for Two Novel Computer Architectures |
DATE
2003
IEEE
14 years 20 days ago
2003
IEEE
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
ASPLOS
1989
ACM
13 years 11 months ago
1989
ACM
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
IAT
2003
IEEE
14 years 19 days ago
2003
IEEE
This paper presents MPIAB, an agent based architecture for parallel processing. The architecture is developed to model the functions of standard MPI using java agents. It remedies...
TC
2010
13 years 2 months ago
2010
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
ARITH
2005
IEEE
13 years 9 months ago
2005
IEEE
This paper presents a novel error-free (infinite-precision) architecture for the fast implementation of both 2-D Discrete Cosine Transform and Inverse DCT. The architecture uses a...