127 search results - page 14 / 26 » Compiler Verification in LF |
CASES
2010
ACM
13 years 5 months ago
2010
ACM
Common generated instruction selections are based on tree pattern matching, but modern and custom architectures feature instructions, which cannot be covered by trees. To overcome...
FDL
2007
IEEE
14 years 1 months ago
2007
IEEE
—This paper presents Anahita Processor Description Language (APDL) for generation of retargetable processor design tool sets. The emphasis is on the applicability of the generate...
EURODAC
1995
IEEE
13 years 11 months ago
1995
IEEE
Verification of image processing systems is mainly done on the basis of image sequence simulations. To achieve high simulation efficiency, our compiled code simulator MSIPC offers...
AIPS
2006
13 years 9 months ago
2006
In AI Planning, as well as Verification, a successful method is to compile the application into boolean satisfiability (SAT), and solve it with state-of-the-art DPLL-based procedu...
ICFP
2005
ACM
14 years 7 months ago
2005
ACM
We describe a monadic interface to low-level hardware features that is a suitable basis for building operating systems in Haskell. The interface includes primitives for controllin...