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» Compiling Erlang to Scheme
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129
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DATE
2003
IEEE
97views Hardware» more  DATE 2003»
15 years 9 months ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
166
Voted
ISADS
2003
IEEE
15 years 9 months ago
A GUI Approach to Programming of TMO Frames and Design of Real-Time Distributed Computing Software
An advanced high-level approach for programming of real-time distributed computing applications, the TMO (Time-triggered Message-triggered Object) programming and specification sc...
K. H. Kim, Seok-Joong Kang
117
Voted
IPPS
1998
IEEE
15 years 8 months ago
Partitioned Schedules for Clustered VLIW Architectures
This paper presents results on a new approach to partitioning a modulo-scheduled loop for distributed execution on parallel clusters of functional units organized as a VLIW machin...
Marcio Merino Fernandes, Josep Llosa, Nigel P. Top...
119
Voted
MICRO
1993
IEEE
93views Hardware» more  MICRO 1993»
15 years 7 months ago
Speculative execution exception recovery using write-back suppression
Compiler-controlled speculative execution has been shown to be e ective in increasing the availableinstruction level parallelismILP found in non-numeric programs. An importantpr...
Roger A. Bringmann, Scott A. Mahlke, Richard E. Ha...
123
Voted
DAC
2005
ACM
15 years 5 months ago
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
Ho Young Kim, Tag Gon Kim