Sciweavers

    559 search results - page 12 / 112
    » Compiling Image Processing Applications to Reconfigurable Ha...
    Sort
    View
    CAMP
    2005
    IEEE
    174views Computer Architecture» more  CAMP 2005»
    Development of a Bit-Level Compiler for Massively Parallel Vision Chips
    14 years 1 months ago
    Development of a Bit-Level Compiler for Massively Parallel Vision Chips
    Download  www.k2.t.u-tokyo.ac.jp
    Abstract— An image sensor in which each pixel has a processing element is called a vision chip. The vision chip can perform real-time visual processing at a high frame rate of 10...
    Takashi Komuro, Shingo Kagami, Masatoshi Ishikawa,...
    claim paper
    Read More »
    CATA
    2003
    195views Computer Science» more  CATA 2003»
    A Genetic Algorithm Approach to Static Task Scheduling in a Reconfigurable Hardware Environment
    13 years 9 months ago
    A Genetic Algorithm Approach to Static Task Scheduling in a Reconfigurable Hardware Environment
    Download  coen.boisestate.edu
    This paper presents a basic framework for applying static task scheduling techniques to arbitrarily-structured task systems whose targeted execution environment is comprised of fi...
    Sin Ming Loo, B. Earl Wells, J. D. Winningham
    claim paper
    Read More »
    DATE
    2010
    IEEE
    166views Hardware» more  DATE 2010»
    A special-purpose compiler for look-up table and code generation for function evaluation
    14 years 21 days ago
    A special-purpose compiler for look-up table and code generation for function evaluation
    Download  www.date-conference.com
    Abstract—Elementary functions are extensively used in computer graphics, signal and image processing, and communication systems. This paper presents a special-purpose compiler th...
    Yuanrui Zhang, Lanping Deng, Praveen Yedlapalli, S...
    claim paper
    Read More »
    ERSA
    2009
    147views Hardware» more  ERSA 2009»
    Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
    13 years 5 months ago
    Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
    Download  eecs.wsu.edu
    Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
    Kylan Robinson, José G. Delgado-Frias
    claim paper
    Read More »
    ERSA
    2006
    197views Hardware» more  ERSA 2006»
    A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System
    13 years 9 months ago
    A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System
    Download  ww1.ucmss.com
    High frame rate video capture and image processing is an important capability for applications in defense and homeland security where incoming missiles must be detected in very sh...
    Vinay Sriram, David Kearney
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.