Sciweavers

559 search results - page 17 / 112
» Compiling Image Processing Applications to Reconfigurable Ha...
Sort
View
EH
1999
IEEE
122views Hardware» more  EH 1999»
13 years 12 months ago
The MorphoSys Dynamically Reconfigurable System-on-Chip
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reco...
Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Ba...
ERSA
2010
115views Hardware» more  ERSA 2010»
13 years 5 months ago
Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware
Research in communication networks has shown that the Internet architecture is not sufficient for modern communication areas such as the interconnection networks of super computing...
Enno Lübbers, Marco Platzner, Christian Pless...
SAMOS
2010
Springer
13 years 6 months ago
Accelerating high-level engineering computations by automatic compilation of Geometric Algebra to hardware accelerators
Abstract—Geometric Algebra (GA), a generalization of quaternions, is a very powerful form for intuitively expressing and manipulating complex geometric relationships common to en...
Jens Huthmann, Peter Muller, Florian Stock, Dietma...
TACO
2008
130views more  TACO 2008»
13 years 7 months ago
Efficient hardware code generation for FPGAs
r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach i...
Zhi Guo, Walid A. Najjar, Betul Buyukkurt
IJES
2007
79views more  IJES 2007»
13 years 7 months ago
Energy-aware compilation and hardware design for VLIW embedded systems
Abstract: Tomorrow’s embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption const...
José L. Ayala, Marisa López-Vallejo,...