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2004
Springer
14 years 1 months ago
An Integer Linear Programming Approach to Classify the Communication in Process Networks
New embedded signal processing architectures are emerging that are composed of loosely coupled heterogeneous components like CPUs or DSPs, specialized IP cores, reconfigurable uni...
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
RSP
2000
IEEE
156views Control Systems» more  RSP 2000»
14 years 1 days ago
Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems
Dataflow programming has proven to be popular for representing applications in rapid prototyping tools for digital signal processing (DSP); however, existing dataflow design tools...
Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya
ERSA
2004
129views Hardware» more  ERSA 2004»
13 years 9 months ago
A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs
Platform FPGAs incorporate many different components, such as processor core(s), reconfigurable logic, memory, etc., onto a single chip. When an application is synthesized on platf...
Jingzhao Ou, Viktor K. Prasanna
DSD
2008
IEEE
165views Hardware» more  DSD 2008»
14 years 2 months ago
Application Analysis for Parallel Processing
Effective mapping of multimedia applications on massively parallel embedded systems is a challenging demand in the domain of compiler design. The software implementations of emerg...
Muhammad Rashid, Damien Picard, Bernard Pottier
DATE
2003
IEEE
97views Hardware» more  DATE 2003»
14 years 29 days ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy