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DATE
2009
IEEE
122views Hardware» more  DATE 2009»
14 years 2 months ago
Model-based synthesis and optimization of static multi-rate image processing algorithms
Abstract—High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special p...
Joachim Keinert, Hritam Dutta, Frank Hannig, Chris...
DAC
2007
ACM
14 years 8 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid
APPINF
2003
13 years 9 months ago
A Multithreaded Compiler Backend for High-level Array Programming
Whenever large homogeneous data structures need to be processed in a non-trivial way, e.g. in computational sciences, image processing, or system simulation, high-level array prog...
Clemens Grelck
ICCAD
2007
IEEE
157views Hardware» more  ICCAD 2007»
14 years 4 months ago
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
—In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The propos...
Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei ...
ICIP
2006
IEEE
14 years 9 months ago
Hardware Computation of Moment Functions in a Silicon Retina using Binary Patterns
We present in this paper a method for implementing moment functions in a CMOS retina for shape recognition applications. The method is based on the use of binary patterns and it a...
Olivier Aubreton, Lew Fock Chong Lew Yan Voon, Guy...