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ICS
2009
Tsinghua U.
14 years 3 months ago
High-performance CUDA kernel execution on FPGAs
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
Alexandros Papakonstantinou, Karthik Gururaj, John...
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
14 years 1 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
FPL
2006
Springer
211views Hardware» more  FPL 2006»
14 years 20 days ago
Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony's PlayStation 2 vector units offer scope for hardware acceleration of applications. We compa...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...
QNS
1996
13 years 10 months ago
Real Inferno
Inferno is an operating system well suited to applications that need to be portable, graphical, and networked. This paper describes the fundamental oating point facilities of the...
Eric Grosse
ISCAPDCS
2003
13 years 10 months ago
Optimal Graph Transformation Assuming Alternate Scheduling Models
Many computation-intensive iterative or recursive applications commonly found in digital signal processing and image processing applications can be represented by data-flow graph...
Timothy W. O'Neil