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132
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VLSISP
2008
123views more  VLSISP 2008»
15 years 3 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...
142
Voted
IJPP
2000
94views more  IJPP 2000»
15 years 3 months ago
Path Analysis and Renaming for Predicated Instruction Scheduling
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
Lori Carter, Beth Simon, Brad Calder, Larry Carter...
132
Voted
PVLDB
2008
134views more  PVLDB 2008»
15 years 2 months ago
Evita raced: metacompilation for declarative networks
Declarative languages have recently been proposed for many new applications outside of traditional data management. Since these are relatively early research efforts, it is import...
Tyson Condie, David Chu, Joseph M. Hellerstein, Pe...
SAMOS
2010
Springer
15 years 1 months ago
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
Igor Böhm, Björn Franke, Nigel P. Topham
136
Voted
ACSAC
2004
IEEE
15 years 7 months ago
CTCP: A Transparent Centralized TCP/IP Architecture for Network Security
Many network security problems can be solved in a centralized TCP (CTCP) architecture, in which an organization's edge router transparently proxies every TCP connection betwe...
Fu-Hau Hsu, Tzi-cker Chiueh