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TC
2010
13 years 2 months ago
Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
Holger Lange, Andreas Koch
HIPEAC
2009
Springer
14 years 2 months ago
Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures
Muhammad Umar Farooq, Lizy Kurian John, Margarida ...
ASPDAC
2009
ACM
91views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Thermal-aware post compilation for VLIW architectures
Wen-Wen Hsieh, TingTing Hwang
CASES
2006
ACM
14 years 1 months ago
Compiler optimization of embedded applications for an adaptive SoC architecture
Charles Hardnett, Krishna V. Palem, Yogesh Chobe
SAMOS
2005
Springer
14 years 1 months ago
Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures
Stefan Farfeleder, Andreas Krall, R. Nigel Horspoo...