1198 search results - page 32 / 240 » Compiling for EDGE Architectures |
TCAD
2008
13 years 8 months ago
2008
This paper explores, develops, and investigates several bypass-sensitive compilation techniques to reduce the register file power by reducing the access frequency to the register f...
ICTAI
2008
IEEE
14 years 3 months ago
2008
IEEE
A number of compact representation forms that are investigated in the knowledge compilation community are utilized in interactive product configuration and other forms of decisio...
SAMOS
2004
Springer
14 years 2 months ago
2004
Springer
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...
FPL
2009
Springer
14 years 1 months ago
2009
Springer
Multitasking reconfigurable computers with one or more reconfigurable processors are being used increasingly during the past few years. One of the major challenges in such systems...
PLDI
1995
ACM
14 years 10 days ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...