Sciweavers

1198 search results - page 33 / 240
» Compiling for EDGE Architectures
Sort
View
CAMP
2005
IEEE
14 years 2 months ago
Development of a Bit-Level Compiler for Massively Parallel Vision Chips
Abstract— An image sensor in which each pixel has a processing element is called a vision chip. The vision chip can perform real-time visual processing at a high frame rate of 10...
Takashi Komuro, Shingo Kagami, Masatoshi Ishikawa,...
ENTCS
2007
108views more  ENTCS 2007»
13 years 8 months ago
Simulating and Compiling Code for the Sequential Quantum Random Access Machine
We present the SQRAM architecture for quantum computing, which is based on Knill’s QRAM model. We detail a suitable instruction set, which implements a universal set of quantum ...
Rajagopal Nagarajan, Nikolaos Papanikolaou, David ...
CLUSTER
2008
IEEE
14 years 3 months ago
Intelligent compilers
—The industry is now in agreement that the future of architecture design lies in multiple cores. As a consequence, all computer systems today, from embedded devices to petascale ...
John Cavazos
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
14 years 2 months ago
Constructing portable compiled instruction-set simulators: an ADL-driven approach
Instruction set simulators are common tools used for the development of new architectures and embedded software among countless other functions. This paper presents a framework th...
Joseph D'Errico, Wei Qin
IH
2005
Springer
14 years 2 months ago
Data Hiding in Compiled Program Binaries for Enhancing Computer System Performance
Abstract. Information hiding has been studied in many security applications such as authentication, copyright management and digital forensics. In this work, we introduce a new app...
Ashwin Swaminathan, Yinian Mao, Min Wu, Krishnan K...