1198 search results - page 47 / 240 » Compiling for EDGE Architectures |
WMPI
2004
ACM
14 years 2 months ago
2004
ACM
The Opie Project aims to develop a compiler to transform C codes written for row-major matrix representation into equivalent codes for Morton-order matrix representation, and to a...
ISCAS
2005
IEEE
14 years 2 months ago
2005
IEEE
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
PPOPP
2005
ACM
14 years 2 months ago
2005
ACM
Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduc...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
CDES
2008
13 years 10 months ago
2008
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...