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CC
2009
Springer
153views System Software» more  CC 2009»
13 years 6 months ago
From Specification to Optimisation: An Architecture for Optimisation of Java Bytecode
We present the architecture of the Rosser toolkit that allows optimisations to be specified in a domain specific language, then compiled and deployed towards optimising object prog...
Richard Warburton, Sara Kalvala
CASES
2003
ACM
14 years 2 months ago
Vectorizing for a SIMdD DSP architecture
The Single Instruction Multiple Data (SIMD) model for fine-grained parallelism was recently extended to support SIMD operations on disjoint vector elements. In this paper we demon...
Dorit Naishlos, Marina Biberstein, Shay Ben-David,...
ASPDAC
2008
ACM
97views Hardware» more  ASPDAC 2008»
13 years 11 months ago
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures
Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
PLDI
2004
ACM
14 years 2 months ago
Vectorization for SIMD architectures with alignment constraints
When vectorizing for SIMD architectures that are commonly employed by today’s multimedia extensions, one of the new challenges that arise is the handling of memory alignment. Pr...
Alexandre E. Eichenberger, Peng Wu, Kevin O'Brien
RSP
2000
IEEE
156views Control Systems» more  RSP 2000»
14 years 1 months ago
Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems
Dataflow programming has proven to be popular for representing applications in rapid prototyping tools for digital signal processing (DSP); however, existing dataflow design tools...
Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya