1198 search results - page 72 / 240 » Compiling for EDGE Architectures |
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
IEEEPACT
2000
IEEE
14 years 1 months ago
2000
IEEE
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
EUROPAR
2004
Springer
14 years 2 months ago
2004
Springer
Several optimization techniques are hindered by uncertainties about the control flow in a program, which can generally not be determined by static methods at compile time. We pres...
IFIP
2000
Springer
14 years 15 days ago
2000
Springer
Scientific programs rely heavily on software libraries. This paper describes the limitations of this reliance and shows how it degrades software quality. We offer a solution that u...
FDL
2008
IEEE
13 years 10 months ago
2008
IEEE
In this paper, we propose the design methodology for communication channel templates from formal specification to RTL description. In this flow, design and verification start from...