1198 search results - page 83 / 240 » Compiling for EDGE Architectures |
MICRO
1998
IEEE
14 years 1 months ago
1998
IEEE
This paper proposes a precise approach to register allocation for irregular-register architectures which is based on 0-1 integer programming (IP). Prior work shows that IP registe...
ARC
2007
Springer
14 years 29 days ago
2007
Springer
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
DAC
1997
ACM
14 years 1 months ago
1997
ACM
—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexe...
CGO
2005
IEEE
14 years 2 months ago
2005
IEEE
Register allocation is one of the most important optimizations a compiler performs. Conventional graphcoloring based register allocators are fast and do well on regular, RISC-like...
ISSS
1999
IEEE
14 years 1 months ago
1999
IEEE
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...