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IPPS
2010
IEEE
13 years 8 months ago
Tile QR factorization with parallel panel processing for multicore architectures
To exploit the potential of multicore architectures, recent dense linear algebra libraries have used tile algorithms, which consist in scheduling a Directed Acyclic Graph (DAG) of...
Bilel Hadri, Hatem Ltaief, Emmanuel Agullo, Jack D...
ICIP
1999
IEEE
14 years 11 months ago
An Efficient VLSI Architecture for Separable 2-D Discrete Wavelet Transform
In this paper, we present a VLSI architecture for separable 2-D Discrete Wavelet Transform (DWT). Based on 1-D DWT Recursive Pyramid Algorithm (RPA), a complete 2-D DWT output sch...
Wen-Shiaw Peng, Chen-Yi Lee
GLVLSI
2003
IEEE
177views VLSI» more  GLVLSI 2003»
14 years 3 months ago
Congestion reduction in traditional and new routing architectures
In dense integrated circuit designs, management of routing congestion is essential; an over congested design may be unroutable. Many factors influence congestion: placement, rout...
Ameya R. Agnihotri, Patrick H. Madden
ANCS
2005
ACM
14 years 3 months ago
Architectural impact of stateful networking applications
The explosive and robust growth of the Internet owes a lot to the ”end-to-end principle”, which pushes stateful operations to the end-points. The Internet grew both in traffic...
Javier Verdú, Jorge García-Vidal, Ma...
VLDB
2004
ACM
101views Database» more  VLDB 2004»
14 years 3 months ago
HiFi: A Unified Architecture for High Fan-in Systems
Advances in data acquisition and sensor technologies are leading towards the development of “High Fan-in” architectures: widely distributed systems whose edges consist of nume...
Owen Cooper, Anil Edakkunni, Michael J. Franklin, ...