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ICPPW
2006
IEEE
15 years 10 months ago
Retargeting Image-Processing Algorithms to Varying Processor Grain Sizes
Embedded computing architectures can be designed to meet a variety of application specific requirements. However, optimized hardware can require compiler support to realize the po...
Sam Sander, Linda M. Wills
WCRE
2002
IEEE
15 years 9 months ago
Register Liveness Analysis for Optimizing Dynamic Binary Translation
Dynamic binary translators compile machine code from a source architecture to a target architecture at run time. Due to the hard time constraints of just-in-time compilation only ...
Mark Probst, Andreas Krall, Bernhard Scholz
ASPLOS
1994
ACM
15 years 8 months ago
Reducing Branch Costs via Branch Alignment
Several researchers have proposed algorithms for basic block reordering. We call these branch alignment algorithms. The primary emphasis of these algorithms has been on improving ...
Brad Calder, Dirk Grunwald
JSA
2006
131views more  JSA 2006»
15 years 4 months ago
Bidirectional liveness analysis, or how less than half of the Alpha's registers are used
Interprocedural data flow analyses of executable programs suffer from the conservative assumptions that need to be made because no precise control flow graph is available and beca...
Bjorn De Sutter, Bruno De Bus, Koen De Bosschere
DATE
2008
IEEE
182views Hardware» more  DATE 2008»
15 years 10 months ago
An adaptable FPGA-based System for Regular Expression Matching
In many applications string pattern matching is one of the most intensive tasks in terms of computation time and memory accesses. Network Intrusion Detection Systems and DNA Seque...
Ivano Bonesana, Marco Paolieri, Marco D. Santambro...