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ARC
2007
Springer
150views Hardware» more  ARC 2007»
15 years 8 months ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...
142
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DAC
1997
ACM
15 years 8 months ago
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexe...
Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas
CGO
2005
IEEE
15 years 9 months ago
A Progressive Register Allocator for Irregular Architectures
Register allocation is one of the most important optimizations a compiler performs. Conventional graphcoloring based register allocators are fast and do well on regular, RISC-like...
David Koes, Seth Copen Goldstein
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 8 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
CASCON
1996
111views Education» more  CASCON 1996»
15 years 5 months ago
A hybrid process for recovering software architecture
A large portion of the software used in industry today is legacy software. Legacy systems often evolve into dicult to maintain systems whose original design has been lost or else ...
Vassilios Tzerpos, Richard C. Holt