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JVM
2004
103views Education» more  JVM 2004»
15 years 5 months ago
The Virtual Processor: Fast, Architecture-Neutral Dynamic Code Generation
Tools supporting dynamic code generation tend too be low-level (leaving much work to the client application) or too intimately related with the language/system in which they are u...
Ian Piumarta
MICRO
1995
IEEE
72views Hardware» more  MICRO 1995»
15 years 7 months ago
Dynamic rescheduling: a technique for object code compatibility in VLIW architectures
Lack of object code compatibility in VLIW architectures is a severe limit to their adoption as a generalpurpose computing paradigm. Previous approaches include hardware and softwa...
Thomas M. Conte, Sumedh W. Sathaye
SAMOS
2004
Springer
15 years 9 months ago
Synchronous Transfer Architecture (STA)
This paper presents a novel micro-architecture for high-performance and low-power DSPs. The underlying Synchronous Transfer Architecture (STA) fills the gap between SIMD-DSPs and ...
Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil...
CC
2009
Springer
153views System Software» more  CC 2009»
15 years 1 months ago
From Specification to Optimisation: An Architecture for Optimisation of Java Bytecode
We present the architecture of the Rosser toolkit that allows optimisations to be specified in a domain specific language, then compiled and deployed towards optimising object prog...
Richard Warburton, Sara Kalvala
CASES
2003
ACM
15 years 9 months ago
Vectorizing for a SIMdD DSP architecture
The Single Instruction Multiple Data (SIMD) model for fine-grained parallelism was recently extended to support SIMD operations on disjoint vector elements. In this paper we demon...
Dorit Naishlos, Marina Biberstein, Shay Ben-David,...