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ASPDAC
2008
ACM
97views Hardware» more  ASPDAC 2008»
15 years 6 months ago
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures
Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
PLDI
2004
ACM
15 years 9 months ago
Vectorization for SIMD architectures with alignment constraints
When vectorizing for SIMD architectures that are commonly employed by today’s multimedia extensions, one of the new challenges that arise is the handling of memory alignment. Pr...
Alexandre E. Eichenberger, Peng Wu, Kevin O'Brien
ICCAD
2001
IEEE
91views Hardware» more  ICCAD 2001»
16 years 27 days ago
A System for Synthesizing Optimized FPGA Hardware from MATLAB
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
Malay Haldar, Anshuman Nayak, Alok N. Choudhary, P...
LCTRTS
2005
Springer
15 years 9 months ago
Generation of permutations for SIMD processors
Short vector (SIMD) instructions are useful in signal processing, multimedia, and scientific applications. They offer higher performance, lower energy consumption, and better res...
Alexei Kudriavtsev, Peter M. Kogge
IEEEINTERACT
2003
IEEE
15 years 9 months ago
Procedure Cloning and Integration for Converting Parallelism from Coarse to Fine Grain
This paper introduces a method for improving program run-time performance by gathering work in an application and executing it efficiently in an integrated thread. Our methods ext...
Won So, Alexander G. Dean