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» Compiling for vector-thread architectures
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114
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APCSAC
2005
IEEE
15 years 8 months ago
Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty
Abstract. Power-balanced instruction scheduling for Very Long Instruction Word (VLIW) processors is an optimization problem which requires a good instruction-level power model for ...
Shu Xiao, Edmund Ming-Kit Lai, A. Benjamin Premkum...
DSN
2005
IEEE
15 years 8 months ago
Effective Testing and Debugging Techniques for a Group Communication System
View-oriented group communication is an important and widely used building block for constructing highlyavailable fault-tolerant systems. Unfortunately, groupcommunication based s...
Eitan Farchi, Gabriel Kliot, Yoel Krasny, Alex Kri...
116
Voted
LCTRTS
2005
Springer
15 years 8 months ago
Probabilistic source-level optimisation of embedded programs
Efficient implementation of DSP applications is critical for many embedded systems. Optimising C compilers for embedded processors largely focus on code generation and instructio...
Björn Franke, Michael F. P. O'Boyle, John Tho...
OOPSLA
2005
Springer
15 years 8 months ago
A delta-driven execution model for semantic computing
We describe (and demonstrate) the execution model of a computing platform where computation is both incremental and data-driven. We call such an approach delta-driven. The platfor...
Roly Perera, Jeff Foster, György Koch
134
Voted
PPDP
2005
Springer
15 years 8 months ago
Self-tuning resource aware specialisation for prolog
The paper develops a self-tuning resource aware partial evaluation technique for Prolog programs, which derives its own control strategies tuned for the underlying computer archit...
Stephen-John Craig, Michael Leuschel