931 search results - page 36 / 187 » Compiling for vector-thread architectures |
132
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ISCAS
2005
IEEE
15 years 8 months ago
2005
IEEE
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
142
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PPOPP
2005
ACM
15 years 8 months ago
2005
ACM
Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduc...
140
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IPPS
2006
IEEE
15 years 8 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
124
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CDES
2008
15 years 3 months ago
2008
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
136
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FECS
2010
15 years 12 days ago
2010
In this paper, we present a method to help teach computer architecture (or computer organization) by developing an in class system where the students, themselves, compile high-leve...