34 search results - page 6 / 7 » Compiling scheme to JVM bytecode: : a performance study |
CONCURRENCY
2006
13 years 7 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
ICCS
2004
Springer
14 years 23 days ago
2004
Springer
On cc-NUMA multi-processors, the non-uniformity of main memory latencies motivates the need for co-location of threads and data. We call this special form of data locality, geogra...
TLCA
2009
Springer
14 years 1 months ago
2009
Springer
Types play an important role both in reasoning about Haskell and for its implementation. For example, the Glasgow Haskell Compiler performs certain fusion transformations that are...
ISCA
1999
IEEE
13 years 11 months ago
1999
IEEE
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...