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JACM
2002
163views more  JACM 2002»
13 years 7 months ago
Formal verification of standards for distance vector routing protocols
We show how to use an interactive theorem prover, HOL, together with a model checker, SPIN, to prove key properties of distance vector routing protocols. We do three case studies: ...
Karthikeyan Bhargavan, Davor Obradovic, Carl A. Gu...
ATVA
2007
Springer
134views Hardware» more  ATVA 2007»
13 years 11 months ago
Formal Modeling and Verification of High-Availability Protocol for Network Security Appliances
One of the prerequisites for information society is secure and reliable communication among computing systems. Accordingly, network security appliances become key components of inf...
Moonzoo Kim
HYBRID
1998
Springer
13 years 11 months ago
Formal Verification of Safety-Critical Hybrid Systems
This paper investigates how formal techniques can be used for the analysis and verification of hybrid systems [1,5,7,16] -- systems involving both discrete and continuous behavior....
Carolos Livadas, Nancy A. Lynch
DSVIS
1998
Springer
13 years 11 months ago
Pragmatic Formal Design: A Case Study in Integrating Formal Methods into the HCI Development Cycle
Formal modelling, in interactive system design, has received considerably less real use than might have been hoped. Heavy weight formal methods can be expensive to use, with poor c...
Meurig Sage, Chris Johnson
DATE
2005
IEEE
164views Hardware» more  DATE 2005»
14 years 28 days ago
Automated Synthesis of Assertion Monitors using Visual Specifications
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...
Ambar A. Gadkari, S. Ramesh