- This paper presents an approach to obtain reduced hardware and/or delay for synthesizing logic functions using multiplexers. Replication of single control line multiplexer is use...
Rekha K. James, T. K. Shahana, K. Poulose Jacob, S...
d Abstract) Thomas Schwentick and Thomas Zeume TU Dortmund University The finite satisfiability problem for two-variable logic over structures with unary relations and two order re...
In many cases, the addition of metric operators to qualitative temporal logics (TLs) increases the complexity of satisfiability by at least one exponential: while common qualitat...
We present a logical approach to plan recognition that builds on Kautz's theory of keyhole plan recognition, defined as the problem of inferring descriptions of high-level pl...
Abstract. This paper presents a Rewriting Logic framework that formalizes the interactions between Web servers and Web browsers through icating protocol abstracting HTTP. The propo...