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SUTC
2008
IEEE
14 years 4 months ago
Power-Aware Real-Time Scheduling upon Identical Multiprocessor Platforms
In this paper, we address the power-aware scheduling of sporadic constrained-deadline hard real-time tasks using dynamic voltage scaling upon multiprocessor platforms. We propose ...
Vincent Nélis, Joël Goossens, Raymond ...
VLSID
2008
IEEE
93views VLSI» more  VLSID 2008»
14 years 4 months ago
Watermarking Video Clips with Workload Information for DVS
We present a lightweight scheme for watermarking or annotating video clips with information describing the workload that would be incurred while decoding the clip. This informatio...
Yicheng Huang, Samarjit Chakraborty, Ye Wang
ISCA
2007
IEEE
126views Hardware» more  ISCA 2007»
14 years 4 months ago
Comparing memory systems for chip multiprocessors
There are two basic models for the on-chip memory in CMP systems: hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison o...
Jacob Leverich, Hideho Arakida, Alex Solomatnikov,...
CSE
2008
IEEE
13 years 12 months ago
Exploiting Intensive Multithreading for the Efficient Simulation of 3D Seismic Wave Propagation
Parallel computing is widely used for large scale threedimensional simulation of seismic wave propagation. One particularity of most of these simulations is to consider a finite c...
Fabrice Dupros, Hideo Aochi, Ariane Ducellier, Dim...
GLVLSI
2010
IEEE
141views VLSI» more  GLVLSI 2010»
13 years 10 months ago
Energy-efficient redundant execution for chip multiprocessors
Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chi...
Pramod Subramanyan, Virendra Singh, Kewal K. Saluj...