63 search results - page 6 / 13 » Complexity Analysis of H.264 Decoder for FPGA Design |
VTC
2007
IEEE
14 years 1 months ago
2007
IEEE
— In this paper, we characterize the achievable performance of a wavelet encoding-based videophone system, which further compresses and protects the wavelet-based video codec’s...
FPGA
2004
ACM
14 years 1 months ago
2004
ACM
The speedup over a microprocessor that can be achieved by implementing some programs on an FPGA has been extensively reported. This paper presents an analysis, both quantitative a...
CORR
2008
Springer
13 years 7 months ago
2008
Springer
Recent works showed how low-density parity-check (LDPC) erasure correcting codes, under maximum likelihood (ML) decoding, are capable of tightly approaching the performance of an i...
TCOM
2010
13 years 6 months ago
2010
—The optimal performance-complexity tradeoff for error-correcting codes at rates strictly below the Shannon limit is a central question in coding theory. This paper proposes a nu...
DSD
2010
IEEE
13 years 5 months ago
2010
IEEE
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...