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ISCAS
2008
IEEE
110views Hardware» more  ISCAS 2008»
14 years 3 months ago
Non-traditional irregular interconnects for massive scale SoC
— By using self-assembling fabrication techniques at the cellular, molecular, or atomic scale, it is nowadays possible to create functional assemblies in a mainly bottom-up way t...
Christof Teuscher, Anders A. Hansson
PARCO
2003
13 years 10 months ago
Cache Memory Behavior of Advanced PDE Solvers
Three different partial differential equation (PDE) solver kernels are analyzed in respect to cache memory performance on a simulated shared memory computer. The kernels implement...
Dan Wallin, Henrik Johansson, Sverker Holmgren
CORR
2010
Springer
160views Education» more  CORR 2010»
13 years 5 months ago
Routing with Mutual Information Accumulation in Wireless Networks
We investigate optimal routing and scheduling strategies for multi-hop wireless networks with rateless codes. Rateless codes allow each node of the network to accumulate mutual in...
Rahul Urgaonkar, Michael J. Neely
ICCAD
2001
IEEE
111views Hardware» more  ICCAD 2001»
14 years 5 months ago
Congestion Aware Layout Driven Logic Synthesis
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
Thomas Kutzschebauch, Leon Stok
ANNPR
2006
Springer
14 years 12 days ago
Hierarchical Neural Networks Utilising Dempster-Shafer Evidence Theory
Abstract. Hierarchical neural networks show many benefits when employed for classification problems even when only simple methods analogous to decision trees are used to retrieve t...
Rebecca Fay, Friedhelm Schwenker, Christian Thiel,...