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» Complexity-Effective Superscalar Processors
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IPPS
2000
IEEE
13 years 12 months ago
Augmenting Modern Superscalar Architectures with Configurable Extended Instructions
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...
Xianfeng Zhou, Margaret Martonosi
ICCD
1996
IEEE
145views Hardware» more  ICCD 1996»
13 years 11 months ago
Can Trace-Driven Simulators Accurately Predict Superscalar Performance?
There are four crucial issues associated with performance simulators: simulator retargetability, simulator validation, simulation speed and simulation accuracy. This paper documen...
Bryan Black, Andrew S. Huang, Mikko H. Lipasti, Jo...
MICRO
1996
IEEE
81views Hardware» more  MICRO 1996»
13 years 11 months ago
Instruction Scheduling and Executable Editing
Modern microprocessors offer more instruction-level parallelism than most programs and compilers can currently exploit. The resulting disparity between a machine's peak and a...
Eric Schnarr, James R. Larus
EUROMICRO
1998
IEEE
13 years 11 months ago
Data Speculative Multithreaded Architecture
In this paper we present a novel processor microarchitecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dep...
Pedro Marcuello, Antonio González
ISCAPDCS
2001
13 years 9 months ago
Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi