Data Speculative Multithreaded Architecture

In this paper we present a novel processor microarchitecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dependences, the relatively small window size and the instruction fetch bandwidth. The new architecture executes simultaneously multiple threads of control obtained from a single program by means of control speculation techniques that do not require any compiler/user support neither any special feature in the instruction set architecture. The multiple simultaneous threads execute different iterations of the same loop, which require the same fetch bandwidth as a single thread since they share the same code. Inter-thread dependences as well as the values that flow through them are speculated by means of data prediction techniques. The preliminary evaluation results show a significant speed-up when compared with a superscalar processor. In fact, the new processor architecture can achieve an IPC (instructions per cy...

• Type: Conference
• Year: 1998
• Where: EUROMICRO
• Authors: Pedro Marcuello, Antonio González
• Keywords: EUROMICRO 1998, Fetch Bandwidth, Instruction Fetch Bandwidth, Software Engineering, Superscalar Processor