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ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
14 years 4 months ago
An SPU reference model for simulation, random test generation and verification
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
Yukio Watanabe, Balazs Sallay, Brad W. Michael, Da...
DATE
2010
IEEE
124views Hardware» more  DATE 2010»
14 years 3 months ago
Control network generator for latency insensitive designs
—Creating latency insensitive or asynchronous designs from clocked designs has potential benefits of increased modularity and robustness to variations. Several transformations h...
Eliyah Kilada, Kenneth S. Stevens
PTS
2007
106views Hardware» more  PTS 2007»
13 years 11 months ago
A New Method for Interoperability Test Generation
Interoperability testing aims at verifying the possibility for two or more components to communicate correctly while providing the foreseen services. In this paper, we describe a n...
Alexandra Desmoulin, César Viho
AAAI
2004
13 years 11 months ago
Automatic Generation of Artistic Chinese Calligraphy
We introduce a novel intelligent system which can generate new Chinese calligraphic artwork that meets certain aesthetic requirements automatically. In the machine learning phase,...
Songhua Xu, Francis C. M. Lau, Kwok-Wai Cheung, Yu...
ACL
2003
13 years 11 months ago
Integrating Discourse Markers into a Pipelined Natural Language Generation Architecture
Pipelined Natural Language Generation (NLG) systems have grown increasingly complex as architectural modules were added to support language functionalities such as referring expre...
Charles B. Callaway