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ISPDC
2010
IEEE
13 years 6 months ago
Pretty Good Accuracy in Matrix Multiplication with GPUs
—With systems such as Road Runner, there is a trend in super computing to offload parallel tasks to special purpose co-processors, composed of many relatively simple scalar proc...
Matthew Badin, Lubomir Bic, Michael B. Dillencourt...
ISCA
2012
IEEE
244views Hardware» more  ISCA 2012»
11 years 10 months ago
Scheduling heterogeneous multi-cores through performance impact estimation (PIE)
Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order) high-performance cores. The eff...
Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout...
EUROPAR
2005
Springer
14 years 1 months ago
Hierarchical Scheduling for Moldable Tasks
The model of moldable task (MT) was introduced some years ago and has been proved to be an efficient way for implementing parallel applications. It considers a target application ...
Pierre-François Dutot
ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
14 years 2 days ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...
HPCA
2009
IEEE
14 years 8 months ago
Hardware-software integrated approaches to defend against software cache-based side channel attacks
Software cache-based side channel attacks present serious threats to modern computer systems. Using caches as a side channel, these attacks are able to derive secret keys used in ...
Jingfei Kong, Onur Aciiçmez, Jean-Pierre Se...