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» Compressed Code Execution on DSP Architectures
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ASAP
2008
IEEE
119views Hardware» more  ASAP 2008»
13 years 9 months ago
An FPGA architecture for CABAC decoding in manycore systems
Arithmetic coding is an efficient entropy compression method that achieves results close to the entropy limit and it is used in modern standards such as JPEG-2000 and H.264. Arith...
Roberto R. Osorio, Javier D. Bruguera
KAIS
2006
247views more  KAIS 2006»
13 years 7 months ago
XCQ: A queriable XML compression system
XML has already become the de facto standard for specifying and exchanging data on the Web. However, XML is by nature verbose and thus XML documents are usually large in size, a fa...
Wilfred Ng, Wai Yeung Lam, Peter T. Wood, Mark Lev...
DATE
2004
IEEE
122views Hardware» more  DATE 2004»
13 years 10 months ago
Phase Coupled Code Generation for DSPs Using a Genetic Algorithm
The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. Due to the irregular arc...
Markus Lorenz, Peter Marwedel
CORR
2006
Springer
103views Education» more  CORR 2006»
13 years 7 months ago
VXA: A Virtual Architecture for Durable Compressed Archives
Data compression algorithms change frequently, and obsolete decoders do not always run on new hardware and operating systems, threatening the long-term usability of content archiv...
Bryan Ford
SBACPAD
2009
IEEE
155views Hardware» more  SBACPAD 2009»
14 years 1 months ago
SPARC16: A New Compression Approach for the SPARC Architecture
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. ...
Leonardo Luiz Ecco, Bruno Cardoso Lopes, Eduardo C...