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» Computing Maximum Subsequence in Parallel
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ASAP
2005
IEEE
142views Hardware» more  ASAP 2005»
14 years 1 months ago
Decimal Floating-Point Square Root Using Newton-Raphson Iteration
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
Liang-Kai Wang, Michael J. Schulte
ICDCSW
2005
IEEE
14 years 1 months ago
Cluster-Based Intelligent Searching in Unstructured Peer-to-Peer Networks
Existing cluster-based searching schemes in unstructured peer-to-peer (P2P) networks employ flooding/random forwarding on connected dominating sets (CDS) of networks. There exist...
Xiuqi Li, Jie Wu
ICDCSW
2005
IEEE
14 years 1 months ago
Capacity Estimation of Non-Synchronous Covert Channels
Capacity estimation is an important part of covert channel analysis. It measures the severity of a covert channel by estimating the maximum information rate attainable over it. Tr...
Zhenghong Wang, Ruby B. Lee
ISCAS
2005
IEEE
143views Hardware» more  ISCAS 2005»
14 years 1 months ago
Design and FPGA implementation of a structure of evolutionary digital filters for hardware implementation
— In this paper, we design and implement an improved hardware-based evolutionary digital filter (EDF) version 2. The EDF is an adaptive digital filter which is controlled by ad...
Masahide Abe, Hiroki Arai, Masayuki Kawamata
DCOSS
2005
Springer
14 years 1 months ago
Routing Explicit Side Information for Data Compression in Wireless Sensor Networks
Abstract. Two difficulties in designing data-centric routes [2–5] in wireless sensor networks are the lack of reasonably practical data aggregation models and the high computatio...
Huiyu Luo, Gregory J. Pottie