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    DAC
    2009
    ACM
    168views Computer Architecture» more  DAC 2009»
    Analysis and mitigation of process variation impacts on Power-Attack Tolerance
    14 years 9 months ago
    Analysis and mitigation of process variation impacts on Power-Attack Tolerance
    Download  www.rfid-cusp.org
    Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
    Lang Lin, Wayne P. Burleson
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    DAC
    2009
    ACM
    192views Computer Architecture» more  DAC 2009»
    Double patterning lithography friendly detailed routing with redundant via consideration
    14 years 9 months ago
    Double patterning lithography friendly detailed routing with redundant via consideration
    Download  www.cerc.utexas.edu
    In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achi...
    Kun Yuan, Katrina Lu, David Z. Pan
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    DAC
    2008
    ACM
    186views Computer Architecture» more  DAC 2008»
    Type-matching clock tree for zero skew clock gating
    14 years 9 months ago
    Type-matching clock tree for zero skew clock gating
    Download  rd.cycu.edu.tw
    Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
    Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-...
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    DAC
    2007
    ACM
    126views Computer Architecture» more  DAC 2007»
    Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
    14 years 9 months ago
    Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
    Download  www.engr.uconn.edu
    Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
    Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
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    DAC
    2007
    ACM
    131views Computer Architecture» more  DAC 2007»
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    14 years 9 months ago
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    Download  cobweb.ecn.purdue.edu
    This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
    Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
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