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» Computing Over-Approximations with Bounded Model Checking
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CAV
2007
Springer
86views Hardware» more  CAV 2007»
14 years 1 months ago
From Liveness to Promptness
Liveness temporal properties state that something “good” eventually happens, e.g., every request is eventually granted. In Linear Temporal Logic (LTL), there is no a priori bo...
Orna Kupferman, Nir Piterman, Moshe Y. Vardi
ICCAD
2004
IEEE
191views Hardware» more  ICCAD 2004»
14 years 4 months ago
Checking consistency of C and Verilog using predicate abstraction and induction
edicate Abstraction and Induction Edmund Clarke Daniel Kroening June 25, 2004 CMU-CS-04-131 School of Computer Science Carnegie Mellon University Pittsburgh, PA 15213 It is common...
Daniel Kroening, Edmund M. Clarke
ATVA
2008
Springer
144views Hardware» more  ATVA 2008»
13 years 9 months ago
Tests, Proofs and Refinements
1 : Logic in Specification and Verification (abstract) Natarajan Shankar (SRI) Session Chair : Sungdeok Cha 12 : 00 13 : 00 Lunch 13 : 00 15 : 00 2 : Boolean Modeling of Cell Biolo...
Sriram K. Rajamani
DFG
2004
Springer
13 years 11 months ago
Modeling and Formal Verification of Production Automation Systems
This paper presents the real-time model checker RAVEN and related theoretical background. RAVEN augments the efficiency of traditional symbolic model checking with possibilities to...
Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wo...
QEST
2006
IEEE
14 years 1 months ago
Modeling Fiber Delay Loops in an All Optical Switch
We analyze the effect of a few fiber delay loops on the number of deflections in an all optical packet switch. The switch is based on the ROMEO architecture developed by Alcatel...
Ana Busic, Mouad Ben Mamoun, Jean-Michel Fourneau