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IEEEPACT
2005
IEEE
14 years 1 months ago
Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors
This paper proposes a new hardware technique for using one core of a CMP to prefetch data for a thread running on another core. Our approach simply executes a copy of all non-cont...
Ilya Ganusov, Martin Burtscher
DAGM
2003
Springer
14 years 22 days ago
Locally Optimized RANSAC
A new enhancement of RANSAC, the locally optimized RANSAC (LO-RANSAC), is introduced. It has been observed that, to find an optimal solution (with a given probability), the numbe...
Ondrej Chum, Jiri Matas, Josef Kittler
SSDBM
2000
IEEE
87views Database» more  SSDBM 2000»
13 years 12 months ago
A Tool for Nesting and Clustering Large Objects
In implementations of non-standard database systems, large objects are often embedded within an aggregate of different types, i.e. a tuple. For a given size and access probabilit...
Stefan Dieker, Ralf Hartmut Güting, Miguel Ro...
ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
13 years 11 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
IJDAR
2007
106views more  IJDAR 2007»
13 years 7 months ago
Investigation and modeling of the structure of texting language
Language usage over computer mediated discourses, like chats, emails and SMS texts, significantly differs from the standard form of the language. An urge towards shorter message l...
Monojit Choudhury, Rahul Saraf, Vijit Jain, Animes...