Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors

This paper proposes a new hardware technique for using one core of a CMP to prefetch data for a thread running on another core. Our approach simply executes a copy of all non-control instructions in the prefetching core after they have executed in the primary core. On the way to the second core, each instruction’s output is replaced by a prediction of the likely output that the nth future instance of this instruction will produce. Speculatively executing the resulting instruction stream on the second core issues load requests that the main program will probably reference in the future. Unlike previously proposed thread-based prefetching approaches, our technique does not need any thread spawning points, features an adjustable lookahead distance, does not require complicated analyzers to extract prefetching threads, is recovery-free, and necessitates no storage for the prefetching threads. We demonstrate that for the SPECcpu2000 benchmark suite, our mechanism significantly increases...

• Type: Conference
• Year: 2005
• Where: IEEEPACT
• Authors: Ilya Ganusov, Martin Burtscher
• Keywords: Core Issues Load, Hardware, IEEEPACT 2005, Primary Core, Primary Core Performance