1474 search results - page 251 / 295 » Computing in Memory Architectures for Digital Image Processi... |
ICPP
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper presents a novel stateless, virtualized communication engine for sub-microsecond latency. Using a Field-Programmable-Gate-Array (FPGA) based prototype we show a latency...
HIPC
2007
Springer
14 years 3 months ago
2007
Springer
: The Cell is a heterogeneous multi-core processor, which has eight co-processors, called SPEs. The SPEs can access a common shared main memory through DMA, and each SPE can direct...
HPCA
2005
IEEE
14 years 2 months ago
2005
IEEE
In the past, there have been several denial-of-service (DOS) attacks which exhaust some shared resource (e.g., physical memory, process table, file descriptors, TCP connections) ...
IPPS
2000
IEEE
14 years 1 months ago
2000
IEEE
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
IUI
2004
ACM
14 years 2 months ago
2004
ACM
Analysis of sketched digital ink is often aided by the division of stroke points into perceptually-salient fragments based on geometric features. Fragmentation has many applicatio...