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IPPS
2006
IEEE
14 years 1 months ago
Exploiting processing locality through paging configurations in multitasked reconfigurable systems
FPGA chips in reconfigurable computer systems are used as malleable coprocessors where components of a hardware library of functions can be configured as needed. As the number of ...
T. Taher, Tarek A. El-Ghazawi
ICPADS
1998
IEEE
13 years 12 months ago
A Comparison of Two Torus-Based K-Coteries
We extend a torus-based coterie structure for distributed mutual exclusion to allow k multiple entries in a critical section. In the original coterie, the system nodes are logical...
S. D. Lang, L. J. Mao
HPCA
2009
IEEE
14 years 8 months ago
Architectural Contesting
Previous studies have proposed techniques to dynamically change the architecture of a processor to better suit the characteristics of the workload at hand. However, all such appro...
Hashem Hashemi Najaf-abadi, Eric Rotenberg
IPPS
2006
IEEE
14 years 1 months ago
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processo...
Jaume Abella, Antonio González
JUCS
2006
112views more  JUCS 2006»
13 years 7 months ago
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi