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CCGRID
2007
IEEE
14 years 3 months ago
Adaptive Performance Modeling on Hierarchical Grid Computing Environments
In the past, efficient parallel algorithms have always been developed specifically for the successive generations of parallel systems (vector machines, shared-memory machines, d...
Wahid Nasri, Luiz Angelo Steffenel, Denis Trystram
IPPS
2003
IEEE
14 years 2 months ago
Architectural Frameworks for MPP Systems on a Chip
Advances in fabrication techniques are now enabling new hybrid CPU/FPGA computing resources to be integrated onto a single chip. While these new hybrids promise significant perfor...
David L. Andrews, Douglas Niehaus
IEEEPACT
2002
IEEE
14 years 2 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
MOBICOM
2010
ACM
13 years 9 months ago
CTRL: a self-organizing femtocell management architecture for co-channel deployment
Femtocell technology has been drawing considerable attention as a cost-effective means of improving cellular coverage and capacity. However, under co-channel deployment, femtocell...
Ji-Hoon Yun, Kang G. Shin
PVG
2003
IEEE
138views Visualization» more  PVG 2003»
14 years 2 months ago
Sort-First, Distributed Memory Parallel Visualization and Rendering
While commodity computing and graphics hardware has increased in capacity and dropped in cost, it is still quite difficult to make effective use of such systems for general-purpos...
E. Wes Bethel, Greg Humphreys, Brian E. Paul, J. D...